diff --git a/arch/arm/boot/dts/msm8226.dtsi b/arch/arm/boot/dts/msm8226.dtsi
index 760f466..89c2241 100644
--- a/arch/arm/boot/dts/msm8226.dtsi
+++ b/arch/arm/boot/dts/msm8226.dtsi
@@ -1001,7 +1001,7 @@
 		compatible = "qcom,acpuclk-a7";
 		reg = <0xf9011050 0x8>;
 		reg-names = "rcg_base";
-		a7_cpu-supply = <&apc_vreg_corner>;
+		a7_cpu-supply = <&pm8226_s2>;/*<&apc_vreg_corner>;*/
 	};
 
 	qcom,ocmem@fdd00000 {
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 77baf62..72c74d3 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1922,15 +1922,21 @@ config MSM_CPU_FREQ_SET_MIN_MAX
 config MSM_CPU_FREQ_MAX
 	int "Max CPU Frequency"
 	depends on MSM_CPU_FREQ_SET_MIN_MAX
-	default 384000
+	default 1190400
 
 config MSM_CPU_FREQ_MIN
 	int "Min CPU Frequency"
 	depends on MSM_CPU_FREQ_SET_MIN_MAX
-	default 245760
+	default 300000
 
 endif # CPU_FREQ_MSM
 
+config USERSPACE_VOLTAGE_CONTROL
+	bool "Enable Userspace CPU Voltage Control"
+	default y
+	help
+	  Userspace Voltage Control
+
 config MSM_AVS_HW
 	bool "Enable Adaptive Voltage Scaling (AVS)"
 	default n
diff --git a/arch/arm/mach-msm/acpuclock-8226.c b/arch/arm/mach-msm/acpuclock-8226.c
index 0e2ae10..a9a2357 100644
--- a/arch/arm/mach-msm/acpuclock-8226.c
+++ b/arch/arm/mach-msm/acpuclock-8226.c
@@ -71,13 +71,13 @@ static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p1[] = {
 };
 
 static struct clkctl_acpu_speed acpu_freq_tbl_8226_1p2[] = {
-	{ 1,  300000, PLL0,    4, 2,   CPR_CORNER_SVS,    0, 4 },
-	{ 1,  384000, ACPUPLL, 5, 2,   CPR_CORNER_SVS,    0, 4 },
-	{ 1,  600000, PLL0,    4, 0,   CPR_CORNER_NORMAL, 0, 6 },
-	{ 1,  787200, ACPUPLL, 5, 0,   CPR_CORNER_NORMAL, 0, 6 },
-	{ 1,  998400, ACPUPLL, 5, 0,   CPR_CORNER_TURBO,  0, 7 },
-	{ 1, 1094400, ACPUPLL, 5, 0,   CPR_CORNER_TURBO,  0, 7 },
-	{ 1, 1190400, ACPUPLL, 5, 0,   CPR_CORNER_TURBO,  0, 7 },
+	{ 1,  300000, PLL0,    4, 2,   1140000,    1140000, 4 },
+	{ 1,  384000, ACPUPLL, 5, 2,   1140000,    1140000, 4 },
+	{ 1,  600000, PLL0,    4, 0,   1150000,    1150000, 6 },
+	{ 1,  787200, ACPUPLL, 5, 0,   1150000,    1150000, 6 },
+	{ 1,  998400, ACPUPLL, 5, 0,   1280000,    1280000, 7 },
+	{ 1, 1094400, ACPUPLL, 5, 0,   1280000,    1280000, 7 },
+	{ 1, 1190400, ACPUPLL, 5, 0,   1280000,    1280000, 7 },
 	{ 0 }
 };
 
@@ -136,7 +136,7 @@ static struct acpuclk_drv_data drv_data = {
 	.pvs_tables = pvs_tables_8226,
 	.current_speed = &(struct clkctl_acpu_speed){ 0 },
 	.bus_scale = &bus_client_pdata,
-	.vdd_max_cpu = CPR_CORNER_TURBO,
+	.vdd_max_cpu = 1280000,
 	.src_clocks = {
 		[PLL0].name = "gpll0",
 		[ACPUPLL].name = "a7sspll",
diff --git a/arch/arm/mach-msm/acpuclock-cortex.c b/arch/arm/mach-msm/acpuclock-cortex.c
index e0cadf2..8d19638 100644
--- a/arch/arm/mach-msm/acpuclock-cortex.c
+++ b/arch/arm/mach-msm/acpuclock-cortex.c
@@ -288,6 +288,69 @@ static unsigned long acpuclk_cortex_get_rate(int cpu)
 	return priv->current_speed->khz;
 }
 
+#ifdef CONFIG_USERSPACE_VOLTAGE_CONTROL
+
+#define MAX_VDD_CPU 1300
+#define MIN_VDD_CPU 900
+
+int get_num_freqs(void)
+{
+	int i;
+	int count = 0;
+
+	for (i = 0; priv->freq_tbl[i].use_for_scaling; i++)
+		count++;
+
+	return count;
+}
+
+ssize_t acpuclk_get_vdd_levels_str(char *buf) 
+{
+
+	int i, len = 0;
+
+	if (buf) {
+		for (i = 0; priv->freq_tbl[i].khz; i++) {
+			if (priv->freq_tbl[i].use_for_scaling) {
+				len += sprintf(buf + len, "%umhz: %i mV\n", priv->freq_tbl[i].khz/1000,
+					priv->freq_tbl[i].vdd_cpu/1000);
+			}
+		}
+	}
+	return len;
+}
+
+ssize_t acpuclk_set_vdd(char *buf) 
+{
+	unsigned int cur_volt;
+	char size_cur[get_num_freqs()];
+	int i;
+	int ret = 0;
+
+	if (buf) {			
+		for (i = 0; priv->freq_tbl[i].use_for_scaling; i++) {
+			ret = sscanf(buf, "%d", &cur_volt);
+
+			if (ret != 1)
+				return -EINVAL;
+
+			if (cur_volt > MAX_VDD_CPU || cur_volt < MIN_VDD_CPU) {
+				printk("Voltage Control: You have set a voltage which is out of range: %i mV !\n", cur_volt);
+				return -EINVAL				
+			}
+
+			priv->freq_tbl[i].vdd_cpu = cur_volt*1000;
+
+			ret = sscanf(buf, "%s", size_cur);
+			buf += (strlen(size_cur)+1);
+			printk("CPU: New UV-Settings: %i mV for %u mhz\n", priv->freq_tbl[i].vdd_cpu/1000, priv->freq_tbl[i].khz/1000);
+		}
+	}
+	return ret;
+}
+
+#endif
+
 #ifdef CONFIG_CPU_FREQ_MSM
 static struct cpufreq_frequency_table freq_table[30];
 
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index 4e189c7..19126d0 100644
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -660,6 +660,22 @@ static ssize_t show_bios_limit(struct cpufreq_policy *policy, char *buf)
 	return sprintf(buf, "%u\n", policy->cpuinfo.max_freq);
 }
 
+#ifdef CONFIG_USERSPACE_VOLTAGE_CONTROL
+extern ssize_t acpuclk_get_vdd_levels_str(char *buf);
+extern void acpuclk_set_vdd(const char *buf);
+
+static ssize_t show_UV_mV_table(struct cpufreq_policy *policy, char *buf) 
+{
+	return acpuclk_get_vdd_levels_str(buf);
+}
+
+static ssize_t store_UV_mV_table(struct cpufreq_policy *policy, const char *buf, size_t count) 
+{
+	acpuclk_set_vdd(buf);
+	return count;
+}
+#endif
+
 cpufreq_freq_attr_ro_perm(cpuinfo_cur_freq, 0400);
 cpufreq_freq_attr_ro(cpuinfo_min_freq);
 cpufreq_freq_attr_ro(cpuinfo_max_freq);
@@ -675,6 +691,9 @@ cpufreq_freq_attr_rw(scaling_min_freq);
 cpufreq_freq_attr_rw(scaling_max_freq);
 cpufreq_freq_attr_rw(scaling_governor);
 cpufreq_freq_attr_rw(scaling_setspeed);
+#ifdef CONFIG_USERSPACE_VOLTAGE_CONTROL
+cpufreq_freq_attr_rw(UV_mV_table);
+#endif
 
 static struct attribute *default_attrs[] = {
 	&cpuinfo_min_freq.attr,
@@ -689,6 +708,9 @@ static struct attribute *default_attrs[] = {
 	&scaling_driver.attr,
 	&scaling_available_governors.attr,
 	&scaling_setspeed.attr,
+#ifdef CONFIG_USERSPACE_VOLTAGE_CONTROL
+	&UV_mV_table.attr,
+#endif
 	NULL
 };